FEATURES
• FUNCTIONS
• Instruction cycle: 16.6 ns (MIN.)
Operation clock: 60 MHz
External clock: 60, 30, 20, 15, 7.5 MHz
Crystal: 60 MHz
• On-chip PLL to provide higher operation clock than the external clock
• Dual load/store
• Hardware loop function
• Conditional execution
• Executes product-sum operation in one instruction cycle
• PROGRAMMING
• 16 bits ´ 16 bits + 40 bits ® 40 bits multiply accumulator
• 8 general registers (40 bits each)
• 8 ROM/RAM data pointer: each data memory area has 4 registers
• 10 source interrupts (external: 4, internal: 6)
• 3 operand instructions (example: R0 = R0 +R1L*R2L)
• Nonpipeline on execution stage
• MEMORY AREAS
• Instruction memory area : 64K words ´ 32 bits
• Data memory areas : 64K words ´ 16 bits ´ 2 (X memory, Y memory)
NEC
9850
SOP-28
NEC
3
NEC
20000
PLCC
RENESAS
983
QFP
RENESAS原现
9600
QFP
NEC
2987
QFP
NEC
11200
SOP24
79000
N/A
NEC
5500
SOP24
NEC
446
BGA
NEC
100500
DIP18
RENESAS/瑞萨
20000
na
RENESAS/瑞萨
880000
QFN
RENESAS/瑞萨
50000
na
NEC
39443
BGAPb
TPS61072DDCR UPD78F0034AGB-8 ISL95520HRZ-T DG452EQ-T1 -E3 DG452EY_T1-E3 S29AL008J55TFIR20 MKW37A512VFT4 XC9536XL-10VQG4 DRV2605LDGSR LP38501TSX-ADJ DG452EQ-T1-E3 UPD78F0034AGB-8EU IRFP9140N ISL95520HRZ-T BSC060N10NS3G IPG20N10S4L-22 MCF5253CVM140 S912ZVMAL3F0MLF TLE985
发布时间:2021-09-30