Features

• Core Arm Cortex-M7 running at 100 MHz in typical conditions

– 16 Kbytes of I-Cache and 16 Kbytes of D-Cache with Error Code Correction (ECC)

– Simple-precision and double-precision HW Floating Point Unit (FPU)

– Memory Protection Unit (MPU) with 16 zones

– DSP Instructions, Thumb®-2 Instruction Set

– Embedded Trace Module (ETM) with instruction trace stream, including Trace Port Interface Unit (TPIU)

• Memories

– 128 Kbytes embedded Flash with built-in ECC (up to 2 errors correction)

– 384 Kbytes embedded SRAM for Tightly Coupled Memory (TCM) interface, running at the same frequency

as the Cortex-M7 with built-in ECC (up to 1 error correction)

– 768 Kbytes embedded Multiport SRAM with built-in ECC (up to 1 error correction) connected to the AHB

system, running at the same frequency as system clock

– Hardened External Memory Controller (HEMC) to address PROM, SRAM and SDRAM with variable data

size (from 8 bits to 48 bits)

• Six independent Chip Selects

• Up to 2 Gbytes of external memory accessible

• Built-in ECC, allowing the correction of up to 2 bits per 32 bits

• System Peripherals

– Built-In Power Fail Detection (PFD), Programmable Supply Monitors and Independent Watchdog for safe operation

– Non-Maskable Interrupt Controller (NMIC)

– Crystal or ceramic resonator oscillators: 3 MHz to 20 MHz main oscillator with failure detection

– RTC with Gregorian calendar and UTC mode, waveform generation in low-power modes

– RTC counter calibration circuitry compensates for 32.768 kHz crystal frequency variations

– 32-bit, low-power Real-time Timer (RTT)

– 4/8/10/12 MHz internal RC oscillator with 4 MHz default frequency for device start-up. In-application trimming access for frequency adjustment

– 32.768 kHz crystal oscillator or embedded 32 kHz RC oscillator as source of Low-Power mode device clock (SCLK)

– One PLL for system clock, and one PLL for peripherals

– One dual-port 32-channel central DMA Controller (XDMAC)

– Four 3-channel 32-bit Timer Counters (TC) with Capture, Waveform, Compare and PWM modes.

Quadrature decoder logic and 2-bit Gray Up/Down Counter for stepper motor

– Two 4-channel 16-bit PWMs with complementary outputs, Dead Time Generator and several fault inputs

per PWM for motor control, two external triggers to manage Power Factor Correction (PFC), DC-DC and lighting control

• Communication Peripherals

– One 10/100 Ethernet MAC (GMAC)

• Energy efficiency support (IEEE® 802.3az standard)

• Ethernet AVB support with IEEE 802.1AS time stamping and IEEE 802.1Qav credit-based trafficshaping

hardware support

• IEEE 1588 Precision Time Protocol (PTP)

– Ten FLEXCOMs, each supporting USART/UART, SPI and TWI/I2C

– Single data rate transfer Quad I/O Serial Peripheral Interface (QSPI)

– CAN Controller compliant with CAN Protocol Version 2.0 Part A, B and ISO 11898-1:2015 and with Bosch

CANFD Specification

– SpaceWire interface with two SpaceWire ports and an Embedded SpaceWire router. Each link has a 200

Mbits/sec bit-rate capability. Integrated RMAP support.

– One 1553 interface with redundant links compliant to MIL-STD-1553B standard. Bus Controller and

Remote Terminal configurations available.

• Safety

– Integrity Check Monitoring (ICM) on memories using Secure Hash Algorithm (SHA)

– FlexProtect Matrix enabling user/privilege operations on peripherals

– Watchdog running on independent uninterruptible monolithic clock

– Clock and power failure detection events routed to normal interrupt or to the Non-Maskable Interrupt (NMI)

controller:

• CPU Frequency Monitor

• Main Crystal Oscillator Failure Detection

• 32.768 kHz Crystal Oscillator Frequency Monitor

• Core Voltage Supply Monitor with internal Power Fail Detection

– Write protection registers on selected peripherals

• Security

– True Random Number Generator (TRNG)

– Secure Hash Algorithm supporting SHA1, SHA224, SHA256, SHA384