[QuickLogic]

Architecture Overview

The QuickRAM family of ESPs (Embedded Standard Products) offers FPGA logic in combination with Dual-Port SRAM modules. The QL4016 is a 16,000 usable PLD gate member of the QuickRAM family of ESPs. QuickRAM ESPs are fabricated on a 0.35 µm four-layer metal process using QuickLogics patented ViaLinkTM technology to provide a unique combination of high performance, high density, low cost, and extreme ease-of-use.

Device Highlights

High Performance & High Density

• 16,000 Usable PLD Gates with 118 I/Os

• 300 MHz 16-bit Counters, 400 MHz Datapaths, 160+ MHz FIFOs

• 0.35 µm four-layer metal non-volatile CMOS process for smallest die sizes

High Speed Embedded SRAM

• 10 dual-port RAM modules, organized in user-configurable 1,152 bit blocks

• 5 ns access times, each port independently accessible

• Fast and efficient for FIFO, RAM, and ROM functions

Easy to Use / Fast Development Cycles

• 100 routable with 100 utilization and complete pin-out stability

• Variable-grain logic cells provide high performance and 100 utilization

• Comprehensive design tools include high quality Verilog/VHDL synthesis

Advanced I/O Capabilities

• Interfaces with both 3.3 V and 5.0 V devices

• PCI compliant with 3.3 V and 5.0 V busses for -1/-2/-3/-4 speed grades

• Full JTAG boundary scan

• I/O Cells with individually controlled Registered Input Path and Output Enables