DESCRIPTION
The HEF4020B is a 14-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (O0, O3 to O13). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. A feature of the HEF4020B is: high speed (typ. 35 MHz at VDD = 15 V).
HEF4020BD
PHI
9600
DIP-16
HEF4020BD
PHI
92
DIP16
HEF4020BD
PHI
962
CDIP
HEF4020BD
PHI
37260
DIP-16
HEF4020BD
PHI
37500
DIP-16/瓷封
HEF4020BD
PHI
890000
TSOP
HEF4020BD
恩XP
5000
CDIP
HEF4020BD
PHI
12
DIP-16/瓷封
HEF4020BD
PHI
3629
CDIP16
HEF4020BD
PHI
12245
CDIP