General Description
The DM74LS279 consists of four individual and independent Set-Reset Latches with active low inputs. Two of the four latches have an additional Sinput ANDed with the primary Sinput. A LOW on any Sinput while the Rinput is HIGH will be stored in the latch and appear on the corresponding Q output as a HIGH. A LOW on the Rinput while the Sinput is HIGH will clear the Q output to a LOW. Simultaneous transition of the Rand Sinputs from LOW-toHIGH will cause the Q output to be indeterminate. Both inputs are voltage level triggered and are not affected by
transition time of the input data.
DM74LS279N
onsemi
12421
16-PDIP
DM74LS279N
20
DIP
DM74LS279N
Fairchild
1
DM74LS279N
原厂
5000
SOP8
DM74LS279N
FAI
65480
DM74LS279N
FAIRCHILD/仙童
10000
DIP16
DM74LS279N
NS
50000
DIP
DM74LS279N
ON/安森美
7800
电联咨询
DM74LS279N
ON Semiconductor
56200
16-DIP
DM74LS279N
NAT
19889
SOP
DM74LS279N
onsemi
12369
16-PDIP
DM74LS279N
onsemi
12421
16-PDIP
DM74LS279N
FSC
20000
NA
DM74LS279N
NS
18
DIP
DM74LS279N
NSC
8888
原装原封