1 Features

Processor cores:

• Up to 2× Dual-core Arm Cortex®-R5F MCU

subsystems operating at up to 800 MHz, highlyintegrated

for real-time processing

– Dual-core Arm Cortex®-R5F clusters support

dual-core and single-core operation

– 32KB ICache and 32KB DCache per R5F core

with SECDED ECC on all memories

– Single-core: 128KB TCM per cluster (128KB

TCM per R5F core)

– Dual-core: 128KB TCM per cluster (64KB TCM

per R5F core)

• 1× Single-core Arm Cortex®-M4F MCU at up to

400 MHz

– 256KB SRAM with SECDED ECC

Memory subsystem:

• Up to 2MB of On-chip RAM (OCSRAM) with

SECDED ECC:

– Can be divided into smaller banks in

increments of 256KB for as many as 8 separate

memory banks

– Each memory bank can be allocated to a single

core to facilitate software task partitioning

• DDR Subsystem (DDRSS)

– Supports LPDDR4, DDR4 memory types

– 16-Bit data bus with inline ECC

– Supports speeds up to 1600 MT/s

System on Chip (SoC) services:

• Device Management Security Controller (DMSC-L)

– Centralized SoC system controller

– Manages system services including initial boot,

security, and clock/reset/power management

– Communication with various processing units

over message manager

– Simplified interface for optimizing unused

peripherals

– On-Chip Debug functionality through JTAG and

Trace interfaces)

• Data Movement Subsystem (DMSS)

– Block Copy DMA (BCDMA)

– Packet DMA (PKTDMA)

– Secure Proxy (SEC_PROXY)

– Ring Accelerator (RINGACC)

• Time Sync Subsystem

– Central Platform Time Sync (CPTS) module

– Timer Manager (TIMERMANAGER) with 1024

timers

– Time Sync and Compare event interrupt routers

Industrial subsystem:

• 2× Gigabit Industrial Communication Subsystems

(PRU_ICSSG)

– Optional support for Profinet IRT, Profinet

RT, EtherNet/IP, EtherCAT, Time-Sensitive

Networking (TSN), and other Networking

Protocols

– Backwards compatibility with 10/100Mb

PRU_ICSS

– Each PRU_ICSSG contains:

• 3× PRU RISC Cores per Slice (2× Slice per

PRU_ICSSG)

– PRU General Use core (PRU)

– PRU Real-Time Unit core (PRU-RTU)

– PRU Transmit core (PRU-TX)

• Each PRU core supports the following

features:

– Instruction RAM with ECC

– Broadside RAM

– Multiplier with optional accumulator

(MAC)

– CRC16/32 hardware accelerator

– Byte swap for Big/Little Endian

conversion

– SUM32 hardware accelerator for UDP

checksum

– Task Manager for preemption support

• Up to 2× Ethernet ports

– RGMII (10/100/1000)

– MII (10/100)

• Three Data RAMs with ECC

• 8 banks of 30 × 32-bit register scratchpad

memory

• Interrupt controller and task manager

• 2× 64-bit Industrial Ethernet Peripherals

(IEPs) for time stamping and other time

synchronization functions

• 18× Sigma-Delta Filter Module (SDFM)

interfaces

– Short circuit logic

– Over-current logic

• 6× Multi-protocol position encoder interfaces

• 1× Enhanced Capture Module (ECAP)

• 16550-compatible UART

– Dedicated 192-MHz clock to support 12-

Mbps PROFIBUS

Security:

• Secure Boot supported

– Hardware-enforced Root-of-Trust (RoT)

– Support to switch RoT via backup key

– Support for takeover protection, IP protection,

and anti-roll back protection

• Support for cryptographic acceleration

– Session-aware cryptographic engine with ability

to auto-switch key-material based on incoming

data stream

– DMA support

– Supports cryptographic cores

• AES – 128/192/256-bit key sizes

• 3DES – 56/112/168-bit key sizes

• MD5, SHA1

• SHA2 – 224/256/384/512-bit key sizes

• DRBG with true random number generator

• PKA (Public Key Accelerator) to Assist in

RSA/ECC processing

• Debugging security

– Secure software-controlled debug access

– Security aware debugging

• Secure storage support

• On-the-Fly encryption (OTFE) support for OSPI in

XIP mode

• Networking security support for data (Payload)

encryption/authentication via packet-based

hardware cryptographic engine

• DMSC-L co-processor for security and key

man