Description

The Intersil ACS112MS is a Radiation Hardened Dual J-K Flip-Flop with Set and Reset. The output change states on the negative transition of the clock (CP1N or CP2N).

The ACS112MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of the radiation hardened, high-speed, CMOS/SOS Logic Family.

The ACS112MS is supplied in a 16 lead Ceramic Flatpack (K suffix) or a Ceramic Dual-In-Line Package (D suffix).

Features

• Devices QML Qualified in Accordance with MIL-PRF-38535

• Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96704 and Intersil’sIntersil QM Plan

• 1.25 Micron Radiation Hardened SOS CMOS

• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)

• Single Event Upset (SEU) Immunity: <1 x 10-10 Errors/Bit/Day (Typ)

• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm2/mg

• Dose Rate Upset . . . . . . . . . . . . . . . . >1011 RAD (Si)/s, 20ns Pulse

• Dose Rate Survivability. . . . . . . . . . . >1012 RAD (Si)/s, 20ns Pulse

• Latch-Up Free Under Any Conditions

• Military Temperature Range . . . . . . . . . . . . . . . . . . -55oC to +125oC

• Significant Power Reduction Compared to ALSTTL Logic

• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V

• Input Logic Levels

    - VIL = 30 of VCC Max

    - VIH = 70 of VCC Min

• Input Current ≤ 1µA at VOL, VOH

• Fast Propagation Delay . . . . . . . . . . . . . . . . 21ns (Max), 14ns (Typ)